Wafer level packaging (WLP) generally refers to the technology of packaging an integrated circuit at wafer level, instead of the traditional process of assembling the package of each individual unit after wafer dicing. WLP is essentially a chip-scale packaging (CSP) technology, since the resulting package is practically of the same size as the die. It is appreciated by those of ordinary skill in the art that wafer-level packaging has paved the way for integration of wafer fabrication, packaging, test, and burn-in at wafer level, for streamlining the manufacturing process.
Wafer level packaging extends the wafer fabrication processes to include device interconnection and device protection processes. As currently understood in the art, there are WLP technology classifications that may be defined as redistribution layer and bump technology, encapsulated copper post technology, encapsulated wire bond technology, and encapsulated beam lead technology.
Redistribution layer and bump technology extends the conventional wafer fabrication process with an additional step that deposits a multi-layer thin-film metal rerouting and interconnection system to each device on the wafer. This is achieved using standard photolithography and thin film deposition techniques employed in the device fabrication. This additional level of interconnection redistributes the peripheral bonding pads of each chip to an area array of metal pads that are evenly deployed over the chip's surface. The solder balls or bumps used in connecting the device to the application circuit board are subsequently placed over these pads. Aside from providing external connections for the WLP, the redistribution technique improves reliability by allowing the use of larger and more robust balls for interconnections.
As further presented in a paper by Michael Topper for Future Fab International, a project from MazikMedia, Inc., within a decade wafer level packaging has changed the infrastructure in the semiconductor industry. Integrated passives, 3-D integration and MEMS/MOEMS have adopted the reliable WLP concepts. 3-D integrated systems need less board space in conjunction with reduced interconnection length providing less parasitic effects for high frequency applications. Integrated passive components will further push the WLP processing. The industry wide adoption of WLP will benefit from the flip chip and wafer bumping infrastructure which is currently created at a breathtaking pace, because process technology, process equipment and materials and general modes of thinking bear many similarities. WLP has to change into a complex system integration to face the rapid developments in semiconductors and to satisfy the increasing functionality demanded by consumers.
In addition, well known manufacturing methods include redistributed chip packaging (RCP) which eliminates the need for wire bonds, package substrates, and flip chip bumps, by way of example. Such is desirable for packaging highly miniaturized devices. RCP provides an interconnect buildup technology in which the package is a functional part of a die. In addition, RCP does not utilize blind vias or require thinned die to achieve thin profiles. Such features simplify assembly, lower costs, and provide compatibility with advanced wafer manufacturing processes utilizing low-k interlayer dielectrics. RCP offers advantages in speed, power, and manufacturability that help enable manufacturers to create small, sleek multifunction devices. A desirable reduction in die area saves board space, and a reduction in thickness reduces the board profile. A reduction in materials and processing costs results from the elimination of wire bond and flip chip bump interconnect technologies. There is a reduction in wafer processing and package yield loss due to thin die handling. Die compatible materials that minimize stress and thermal mismatches, while improving reliability and minimizing defects.
Based on current trends and industry demand, it is desirable for the next generation of wafer level packages or modules to be cheaper and smaller for use in future cell phones, by way of example. It is further desirable that their manufacturing process provides greater functionality with improved yields. The present invention is directed to improving the wafer level package and its manufacturing.